Group — turn the current selection into a named composite component (enabled only with a selection). With a single selected custom component it promotes it into the library.

New component (+) — create a new, empty custom component from scratch: name it and it is placed on the canvas (not yet in the library). Double-click it to descend and add inputs/outputs and internal components; then select it and press Group to add it to the library (see §3).

Simulate / Exit — switch between design and simulate mode.

Run / Step / Stop / Reset — simulation controls (see §7). Run also enters simulate mode from design mode and starts running; Space toggles run/pause while simulating.

Simulation settings (gear) — open the simulation settings dialog.

Breadcrumb — the path of components you’ve navigated into (main / adder / …); the ↑ button (or Escape) goes up one level. A template badge marks a library template.

Open / Save JSON — load or save the whole design as a .json file.

Export Verilog — generate synthesizable Verilog from the current design and download it as a .v file (see §8).

Save as default / Clear default — store the current design in the browser’s localStorage as the automatic launch state, or remove it so the app starts empty again.

Clear everything — wipe parts of the design after a confirmation dialog with checkboxes: the component tree (the root sheet) and the “My components” library, where the library can be deleted as a whole (All components) or per category (Uncategorized plus each user-defined category). Everything is checked by default; uncheck what you want to keep (disabled while simulating).

Copy link — copy a shareable URL to the clipboard: the design is gzipped and base64-encoded into a ?d= query parameter, and opening that URL restores the design on launch (see §9).

Settings — open the global settings dialog (lane distance, simulation history size, and history-limit behaviour; see below).

Theme toggle — switch between dark and light.

Components — a tree of the current sheet’s instances. Double-click a composite to enter it; single-click to select it on the canvas.

Ports — the current scope’s terminals (shown first). Add (+) / remove (−) terminals (when the primitive allows it), rename them, reorder by dragging the ⣿ handle, and toggle the inversion checkbox (the negation bubble).

Properties — for the selected component: its name, its type, its primitive properties (e.g. a CLOCK’s Period, a BUS’s Lanes), and an editable terminal list for that component, so you can add/remove/reorder/rename/invert its terminals without entering it. Values commit on Enter or blur.

My components — your composite components. Drag to place; double-click to edit its template; × deletes it. Export / Import exchange your component library as JSON, and Apply to scope / Apply to all (shown when a template is selected) propagate that template’s edits (including its port names) to matching placed instances — in the current scope, or across the whole design. Delete opens a dialog that removes whole library categories (see below). The list scrolls if it grows tall. A category dropdown above the list shows one category at a time; the Move to category dropdown below the buttons moves the selected component to an existing category or ＋ New category… (type a name and press Enter). It is always visible but disabled until a component is selected, and while you are editing a template.

Group dialog — name the new component and its inferred inputs/outputs (press Enter to create).

Simulation settings — default gate delay (ps), the step mode, and the simulation speed.

Settings — the global settings dialog:

Delete dialog — confirm deleting a library template.

Delete categories dialog — opened from the library’s Delete button: it lists every library category (including Uncategorized) with a checkbox, plus a Select all master toggle, so you can delete the whole library or just chosen categories. The list scrolls when it grows past ~15 categories.

Toast — transient messages (e.g. “Input already has a driver”).

In every dialog, Escape cancels/closes it, and the confirmation dialogs pre-focus their primary button so Enter completes the action immediately.

Draw a wire — press an output pin, drag, and release on an input pin.

Re-target / delete a wire — press an input pin that already has a wire, drag, and release on a new input (re-target) or on empty space (delete).

Cut wires to delete — hold Alt and drag across the canvas: a red dashed line is drawn, and on release every wire it crosses is removed. A bus is removed only when the line cuts through all of its lanes. (Unlike Ctrl/Cmd+drag, this deletes rather than splitting, and it can remove many wires at once.)

An input can have at most one driver; dropping a second wire onto a driven input is rejected with a message.

With one or more components selected (or while dragging them), each unconnected terminal that sits near a matching terminal on another component is shown as a dashed orange preview wire. Inputs look for the nearest nearby output, outputs for the nearest nearby unconnected input — the closest within a short distance (about 20 world units) wins, and only width-compatible pairs are matched. The composite’s own input/output port groups are valid targets too.

Press c to wire every previewed match at once (a single undo step). Clear the selection (or press Escape) to dismiss the previews without connecting.

Count — how many copies to place. Each non-chained terminal becomes a count-wide bus (e.g. a full-adder’s A/B/Sum become 4-bit buses for Count = 4).

Orientation — lay the copies out horizontally (left to right) or vertically (top to bottom; the default). The surrounding flow — input port, fan-outs, the copies, fan-ins, output port — is always left-to-right; orientation only affects how the copies are arranged among themselves.

Inputs — for each input, choose Parallel (bus) (one wire per copy, the default) or Common (shared) (one wire delivered to every copy, routed through a NODE join-point). Use Common for a signal all copies share — e.g. the selection line of a word mux built from bit muxes. Chained inputs are already single-wire, so they show as chained and can’t be toggled.

Chains — optional rules that wire one output of each copy to the next copy’s input (copy[i].from → copy[i+1].to). The classic ripple-carry rule is Cout → Cin: the first copy’s Cin and last copy’s Cout become the array’s single-wire terminals. Add several chains for e.g. a shift register.

A floating pulled input reads as a real 1/0 in simulation (instead of x) — so, for example, an unconnected active-high reset can be tied inactive.

In Verilog export a pulled floating input is tied to a constant and is not reported as a floating net.

Like inversion, pull is instance-level and external-only: it lives on the placed instance, never on the template or on a component’s own port groups.

The DFF’s RST input is pulled down by default, so a DFF whose reset is left unconnected behaves as “no reset” rather than floating.

Inputs: 2+ (A, B, … up to H) · Outputs: 1 (Y) · inputs variable

Output is 1 only when all inputs are 1; 0 dominates; x propagates otherwise.

Inputs: 2+ (A, B, …) · Outputs: 1 (Y) · inputs variable

Output is 1 when any input is 1; 1 dominates.

Inputs: 2+ (A, B, …) · Outputs: 1 (Y) · inputs variable

Output is 1 on odd parity (an odd number of inputs are 1).

Inputs: 1 (A) · Outputs: 1 (Y, inverted)

Negates its input. Drawn as a triangle with a bubble (the bubble is the inverted output).

Inputs: 1 (A) · Outputs: 1 (Y)

Passes its input through unchanged. Useful for fan-out / signal cleanup.

Inputs: none · Outputs: 1 (CLK)

A source producing a periodic square wave. Property Period (picoseconds, default 100 000) sets the period. Its frequency (Hz / kHz / MHz) is shown above the component.

Inputs: D, CLK, RST · Outputs: 2 (Q, !Q) · Properties Edge (posedge / negedge, default posedge), Initial value (boolean, default off), Active-high reset (boolean, default on)

A D flip-flop. On the configured Edge of CLK, Q takes the value of D (after a clk-to-q delay); between edges Q holds.

!Q is always the complement of Q.

When RST is asserted (high by default, low with Active-high reset off), Q is forced asynchronously to the Initial value, overriding the clock. On power-on Q starts at the Initial value.

RST is pulled down by default, so leaving it unconnected reads as inactive (no reset) rather than floating.

Inputs: CLK, RST · Outputs: Q bus, or Q0… single wires · Properties Reset (sync / async, default sync), Terminal type (wire / bus, default wire), Width (0–32, default 0)

A binary counter. On each rising edge of CLK the count increments by one, wrapping at its width. Q0 is the least-significant bit.

Reset selects when an asserted RST (active-high) clears the count to zero:

Terminal type picks the output shape: wire gives one single-wire output per counting bit (Q0…Q(n-1)), with the count set by Width (0 uses the default count); bus gives one Q bus whose width is adopted from the connected bus when Width is 0, and pinned to Width lanes otherwise. Changing the terminal type keeps CLK/RST wiring but disconnects the output wires.

RST is pulled down by default, so an unconnected reset reads inactive.

In Verilog export this becomes an always @(posedge clk …) counter (with if (rst) for the chosen reset style) — the FPGA gets real synchronous counting logic rather than a ripple counter built from flip-flops.

Inputs: CLK, RST, DATA (bus) or D0… (single wires) · Outputs: Q bus, or Q0… single wires · Properties Reset (sync / async, default sync), Terminal type (wire / bus, default bus), Width (0–32, default 0)

An n-bit register (an array of 1-bit memory cells). On each rising edge of CLK the register samples DATA into Q (after a clk-to-q delay); between edges Q holds its value. D0/Q0 is the least-significant bit.

Reset selects when an asserted RST (active-high) clears the register to zero:

Terminal type picks the data shape: bus gives one DATA bus input and one Q bus output (always the same width — adopted from the connected bus when Width is 0, and pinned to Width lanes otherwise); wire gives one single-wire D0…/Q0… per bit, with the bit count set by Width (0 uses the default count). Changing the terminal type keeps CLK/RST wiring but disconnects the data and output wires.

RST is pulled down by default, so an unconnected reset reads inactive.

In Verilog export this becomes always @(posedge clk …) q <= data (with if (rst) for the chosen reset style) — a real synchronous register the FPGA can map to flip-flops.

Inputs: 1 (ADDR) · Outputs: 1 (DATA) · Properties Address width (busWidth, default 8, 1–16), Data width (dataWidth, default 8, 1–64), Access (async / sync, default async), Value format (HEX / DEC / BINARY, default HEX)

A read-only memory: put an address on the ADDR bus and the stored word appears on the DATA bus. The Access property picks the read timing: async reads combinationally — there is no clock and no address latching, so DATA follows ADDR like any combinational gate (and resolves before any clock edge); sync adds a CLK input and latches the address + registers the data on a clock edge (one-cycle latency). Any unknown (x) address bit drives all-x data; addresses past the stored contents read 0.

The memory holds 2^AddressWidth words of DataWidth bits each (so an 8-bit address is 256 × 8-bit). Click Edit contents… in the properties panel to open the contents editor:

In Verilog export the ROM follows its Access: async emits a combinational case lookup (distributed LUTs, DATA available before any clock edge), while sync emits an inferred memory (reg mem[] + an initial block + always @(posedge CLK) DATA <= mem[ADDR]), which the FPGA toolchain can implement as block RAM.

Inputs: 2+ (single-wire), default 4 · Outputs: 1 (BUS) · inputs variable

Bundles its n single-wire inputs into one n-wide bus output.

Inputs: 1 (BUS) · Outputs: 2+ (single-wire), default 4 · outputs variable

Splits one n-wide bus input into n single-wire outputs.

Inputs: 1 (BUS, width n) · Outputs: 2 (Y1, Y2)

Splits a bus into two parts. By default it splits evenly (Y1/Y2 each n/2, requiring an even width); the First lanes property (default 0, 0–64) fixes Y1 to that many lanes and gives Y2 the remainder (n − First lanes). 0 means “split evenly”.

Inputs: 2 (A, B) · Outputs: 1 (BUS)

Concatenates two buses into one. By default the two inputs are equal (each m, the output 2m); the First lanes property (default 0, 0–64) fixes A to that many lanes and gives B the remainder (output − First lanes). 0 means “merge evenly”.

Inputs: 1 (A) · Outputs: 1 (Y)

A passthrough that fixes the bus width. Property Lanes (default 8, 1–64) sets the width of both terminals; use it to pin a bus to a specific width regardless of its source. Property Flip (default off) reverses the lane order, so the input’s LSB becomes the output’s MSB (the width is unchanged); a flipped bus shows a small diagonal X in place of its middle lane.

Inputs: 2 (A, B, equal derived width) · Outputs: 1 (EQ)

Compares its two bus inputs bit-for-bit: EQ is 1 when they match, 0 when they differ, and x when either input has an unknown bit. Both inputs adopt the same width (neither is fixed), so the comparator follows whatever width its buses carry.

Inputs: 1 (A) · Outputs: 1 (Y)

A single-wire join point: a filled dot whose input and output terminals coincide, drawn with no labels. It passes its input through unchanged, and multiple wires exit by fan-out from its single output. Drag a wire onto the dot to feed it; press the dot to start another outgoing wire; Alt+press grabs the incoming wire. To move it, drag the ring just around the dot (or region-select it first). The dot is wire-colored, signal-colored in simulation, and red while hovered.

Two shortcuts insert a NODE into an existing wire, splitting it in two:

Inputs: 1 (BUS) · Outputs: none · Properties Mode (HEX / DEC / SIGNED DEC) and Order (asc / desc)

A multi-digit display. Its bus width must be a multiple of 4 and ≤ 64. The Mode controls how the bus bits are decoded:

Inputs: none · Outputs: 1+ · Properties Terminal type (wire / bus, default bus), Initial value (text, default 0), Value format (HEX / DEC / SIGNED DEC / BINARY, default HEX), Order (asc / desc, default asc), and Compact (boolean, default on)

A multi-lane interactive source. In wire mode each output terminal is one switch; in bus mode a single bus output carries one lane per wire. Every lane starts at the Initial value when simulation starts (and shows that state, colored, in design mode). In simulate mode, click an indicator circle to toggle its lane, or use the −/+ step buttons to increment or decrement the whole value.

Initial value is a number entered in the current Value format (signed or unsigned decimal, or hex); Order decides how the typed value maps onto the lanes. In Verilog export a non-exported switch becomes a constant fixed at this value.

Compact renders the switch as a single small box showing its current value (in the instance’s Value format) instead of one circle per lane — useful for wide buses. Its lanes are set via the # badge / set-value dialog or the −/+ buttons rather than individual clicks.

Inputs: 1+ · Outputs: none · Properties Terminal type (wire / bus, default bus), Value format (HEX / DEC / SIGNED DEC / BINARY, default HEX), Order (asc / desc, default asc), and Compact (boolean, default off)

A multi-lane lamp. In wire mode each input terminal is one LED; in bus mode a single bus input lights one LED per lane. Each lane lights when its signal is 1.

Compact renders the LED as a single small box showing the current value of its input (in the instance’s Value format) instead of one circle per lane — useful for wide buses. The value updates during simulation; in design mode (no signal yet) it shows a ? placeholder. Order picks which end of the bus is the least-significant bit for the display.

Inputs: 1 (IN) · Outputs: none · Properties: Pause on trigger, Trigger on

A monitoring tap: it records the signal on whatever it is wired to (a single wire or a whole bus, adopting the connected width) so you can inspect it in the Simulation timeline (§7). It has no effect on the circuit. Probes are not grouped — if you select a probe alongside other components and click Group, the probe stays on the sheet and keeps tapping the new component’s output. A probe is ignored by the Verilog export.

Pause on trigger arms a run pause: when enabled, the simulation stops the moment the probe’s input meets the Trigger on condition. The condition is an edge — RISING_EDGE (0→1), FALLING_EDGE (1→0), or EDGE (either). On a bus input the trigger fires if any lane meets the condition. Only strict 0↔1 transitions count (x never triggers).

Run — enter simulate mode (if not already) and advance the simulation continuously.

Step — advance one step (see Step mode).

Stop — pause a running simulation.

Reset — rebuild the simulation from scratch.

Space — toggle between running and paused while simulating.

Settings — set the default gate delay (ps), the step mode, and the simulation speed.

green — the combinational logic settles within half a clock period.

yellow — it takes more than half a period (it doesn’t settle before the next clock edge).

red — it takes more than a full period (the clock is too fast for the logic).

Wires and terminal markers are colored by their value: red = 1, black = 0, yellow = x.

CLOCK toggles its output on a square wave with its Period.

SWITCHES lanes toggle by clicking their indicator circles (a double-click just toggles twice — it does not enter the component).

LEDS lanes light when their signal is 1.

7-SEG displays the value of each 4-bit nibble of its bus.

PROBE records the signal on its input for the timeline (below).

The horizontal axis is time-proportional: the distance between two events is proportional to the time between them.

Mouse wheel zooms the time axis (anchored at the cursor); press-and-drag on the waveform area pans horizontally; rows that don’t fit scroll vertically.

Drag a probe’s handle/name up or down to reorder it — a bus moves as one unit. The order is remembered while the app is open.

The timeline keeps the last simulation, so you can inspect it after leaving simulate mode.

If the history limit is hit in Stop mode, the simulation pauses and the timeline shows a "`History limit reached`" notice (change the limit or switch to Sliding in Settings).

Enter parses the value (in the chosen radix) and sets the switches, closing the dialog; an out-of-range or malformed value shows an error and stays open.

Escape (or Cancel) closes without changing anything.

The radix chosen in the dialog only affects that dialog — it does not change the instance’s Value format. The instance’s Order is applied when the typed value is mapped onto the lanes.

Quiescent — each Step advances until the circuit settles (no pending events).

Clock-edge — each Step advances to the next clock edge.